Field of the Invention
This invention relates to generating clock signals for electronic devices.
Description of the Related Art
In general, clock synthesizers generate clock signals utilized by a wide variety of electronic products. A typical clock synthesizer utilizes a feedback control system (e.g., a phase-locked loop or a frequency-locked loop) supplied with a fixed frequency reference clock signal by a source such as a crystal oscillator. Although large loop bandwidths suppress more voltage-controlled oscillator noise than lower loop bandwidths and may support higher data rates, loop stability requirements limit maximum loop bandwidth to a fraction of the reference clock frequency FREF (e.g., 0.1×FREF). In addition, conventional phase-locked loops track edge alignment variations of reference clock signals and feedback clock signals thereby further degrading noise performance. Accordingly, improved techniques for reducing or eliminating noise in phase-locked loops and frequency-locked loops are desired.
The use of the same reference symbols in different drawings indicates similar or identical items.